fallback: legalize: G_INSERT_VECTOR

fallback: legalize: G_INSERT_VECTOR_ELT <8 x s8>,s8,s64

Run:	main-04ca53e65f-20261014-113325
Kind:	fallback
Category:	legalize: G_INSERT_VECTOR_ELT <8 x s8>,s8,s64
Occurrences:	18 in 16 configs, 9 test files
Snippet from:	rvp-simd-64.ll @test_insert_vector_8 via llvm-extract
Config:	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
Local check:	reproduces at 04ca53e65f
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

define <8 x i8> @test_insert_vector_8(<8 x i8> %a, i8 %val) {
  %res = insertelement <8 x i8> %a, i8 %val, i32 0
  ret <8 x i8> %res
}

Reproduce:

llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %3:_(<8 x s8>) = G_INSERT_VECTOR_ELT %0:_, %1:_(s8), %4:_(s64) (in function: test_insert_vector_8)
warning: Instruction selection used fallback path for test_insert_vector_8

Occurrences (18):

Input	Function	Config
rvp-simd-64.ll	test_insert_vector_8	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_insert_vector_8_elem3	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
calls.0bbefdd6e3.ll (mutant of calls.ll)	defined_function	`-code-model=large -mtriple=riscv64 -mattr=experimental-zicfilp -verify-machineinstrs`
calls.4ded028f61.ll (mutant of calls.ll)	defined_function	`-code-model=large -mtriple=riscv64 -verify-machineinstrs`
calls.5152d40c05.ll (mutant of calls.ll)	defined_function	`-code-model=small -mtriple=riscv64 -verify-machineinstrs`
calls.a19154f1d8.ll (mutant of calls.ll)	defined_function	`-code-model=medium -mtriple=riscv64 -verify-machineinstrs`
calls.ecd5ad1432.ll (mutant of calls.ll)	defined_function	`-mtriple=riscv64 -verify-machineinstrs`
float-imm.610221dded.ll (mutant of float-imm.ll)	poison	`-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f`
fold-masked-merge.5c3e40f88f.ll (mutant of fold-masked-merge.ll)	masked_merge2	`-mtriple=riscv64 -mattr=+zbb`
fold-masked-merge.8df4983ff6.ll (mutant of fold-masked-merge.ll)	masked_merge2	`-mtriple=riscv64`
half-imm.6bfa3ecc57.ll (mutant of half-imm.ll)	poison	`-mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs -target-abi lp64`
half-imm.c33188cae3.ll (mutant of half-imm.ll)	poison	`-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi lp64f`
half-imm.c9f91ce59d.ll (mutant of half-imm.ll)	poison	`-mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64`
half-imm.e54bbc9690.ll (mutant of half-imm.ll)	poison	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f`
machine-sink-load-immediate.2bef8df126.ll (mutant of machine-sink-load-immediate.ll)	switch_dispatch	`-mtriple=riscv64`
sfb-merge-base-offset.9e8b8a4b2a.ll (mutant of sfb-merge-base-offset.ll)	load_cond_ga_word_zext	`-mtriple=riscv64 -verify-machineinstrs -mattr=+short-forward-branch-iload`
stack-clash-prologue.ceed16580d.ll (mutant of stack-clash-prologue.ll)	f2	`-mtriple=riscv64 -mattr=+m -O2`
switch-width.3ba3fea8da.ll (mutant of switch-width.ll)	trunc_i32	`-O2 -mtriple=riscv64`

Generated 2026-10-15 08:05 UTC.