fallback: legalize: G_LOAD <4 x s16>,p0

Run:	main-04ca53e65f-20261014-113325
Kind:	fallback
Category:	legalize: G_LOAD <4 x s16>,p0
Occurrences:	24 in 4 configs, 1 test files
Snippet from:	rvp-unaligned-load-store.ll @test_store_v4i16_align1 via llvm-extract
Config:	`-mtriple=riscv32 -mattr=+experimental-p`
Local check:	reproduces at 04ca53e65f
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

define void @test_store_v4i16_align1(ptr %a_ptr, ptr %b_ptr) {
  %a = load <4 x i16>, ptr %a_ptr, align 8
  store <4 x i16> %a, ptr %b_ptr, align 1
  ret void
}

Reproduce:

llc -mtriple=riscv32 -mattr=+experimental-p -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+experimental-p -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(<4 x s16>) = G_LOAD %0:_(p0) :: (load (<4 x s16>) from %ir.a_ptr) (in function: test_store_v4i16_align1)
warning: Instruction selection used fallback path for test_store_v4i16_align1

Occurrences (24):

Input	Function	Config
rvp-unaligned-load-store.ll	test_store_v4i16_align1	`-mtriple=riscv32 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v4i16_align2	`-mtriple=riscv32 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v4i16_align4	`-mtriple=riscv32 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_load_v4i16_align1	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i16_align1	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v4i16_align2	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i16_align2	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v4i16_align4	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i16_align4	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i16_align1	`-mtriple=riscv64 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v4i16_align2	`-mtriple=riscv64 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v4i16_align4	`-mtriple=riscv64 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_load_v4i16_align1	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i16_align1	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v4i16_align2	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i16_align2	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v4i16_align4	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i16_align4	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.0f13cde7a9.ll (mutant of rvp-unaligned-load-store.ll)	test_load_v4i16_align1	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.197eb7afcb.ll (mutant of rvp-unaligned-load-store.ll)	test_load_v4i16_align1	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.57cf5d4cee.ll (mutant of rvp-unaligned-load-store.ll)	test_load_v4i16_align2	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.6eac9ed6ca.ll (mutant of rvp-unaligned-load-store.ll)	test_load_v4i16_align1	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.7f89b6829e.ll (mutant of rvp-unaligned-load-store.ll)	test_load_v4i16_align1	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.c2636bc9de.ll (mutant of rvp-unaligned-load-store.ll)	test_load_v4i16_align2	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`

Generated 2026-10-15 08:05 UTC.