fallback: legalize: G_ADD <2 x s32>

Run:main-bc8218b282-20261015-074651
Kind:fallback
Category:legalize: G_ADD <2 x s32>
Occurrences:24 in 2 configs, 5 test files
Snippet from:calling-conv-p-ext-vector.ll @test_cc_v2i32 via llvm-extract
Config:-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
Local check:reproduces at bc8218b282
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

define <2 x i32> @test_cc_v2i32(<2 x i32> %a, <2 x i32> %b) {
  %res = add <2 x i32> %a, %b
  ret <2 x i32> %res
}

Reproduce:

llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(<2 x s32>) = G_ADD %0:_, %1:_ (in function: test_cc_v2i32)
warning: Instruction selection used fallback path for test_cc_v2i32

Occurrences (24):

InputFunctionConfig
calling-conv-p-ext-vector.lltest_cc_v2i32-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-mul-parts-acc-fold.llpmacc_h00-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-mul-parts-acc-fold.llpmacc_h01-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-mul-parts-acc-fold.llpmacc_h11-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-mul-parts-acc-fold.llpmaccu_h00-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-mul-parts-acc-fold.llpmaccu_h01-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-mul-parts-acc-fold.llpmaccu_h11-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-mul-parts-acc-fold.llpmaccsu_h00-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-mul-parts-acc-fold.llpmaccsu_h11-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-32.lltest_pwadd_h-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-32.lltest_pwaddu_h-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_padd_w-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_psh1add_w-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_paaddu_w-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_padd_ws_splat_lhs-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_padd_ws_splat_rhs-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-widening-add-acc.lltest_pwadda_v2i16-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs
rvp-widening-add-acc.lltest_pwaddau_v2i16-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs
calling-conv-p-ext-vector.d5040e51e8.ll (mutant of calling-conv-p-ext-vector.ll)test_cc_v2i32-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-mul-parts-acc-fold.4be1cee1a1.ll (mutant of rvp-mul-parts-acc-fold.ll)pmaccu_h01-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-mul-parts-acc-fold.b46a245aa7.ll (mutant of rvp-mul-parts-acc-fold.ll)pmacc_h00-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-widening-add-acc.167b594017.ll (mutant of rvp-widening-add-acc.ll)test_pwadda_v2i16-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs
rvp-widening-add-acc.167b594017.ll (mutant of rvp-widening-add-acc.ll)test_pwaddau_v2i16-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs
rvp-widening-add-acc.c2cc75374f.ll (mutant of rvp-widening-add-acc.ll)test_pwadda_v2i16-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs

Generated 2026-10-15 08:05 UTC.