fallback: legalize: G

fallback: legalize: G_ADD <4 x s16>

Run:	main-bc8218b282-20261015-074651
Kind:	fallback
Category:	legalize: G_ADD <4 x s16>
Occurrences:	42 in 6 configs, 6 test files
Snippet from:	calling-conv-p-ext-vector.ll @test_cc_v4i16 via llvm-extract
Config:	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
Local check:	reproduces at bc8218b282
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

define <4 x i16> @test_cc_v4i16(<4 x i16> %a, <4 x i16> %b) {
  %res = add <4 x i16> %a, %b
  ret <4 x i16> %res
}

Reproduce:

llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(<4 x s16>) = G_ADD %0:_, %1:_ (in function: test_cc_v4i16)
warning: Instruction selection used fallback path for test_cc_v4i16

Occurrences (42):

Input	Function	Config
calling-conv-p-ext-vector.ll	test_cc_v4i16	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
calling-conv-p-ext-vector.ll	test_exhaust_2xlen_rv32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
calling-conv-p-ext-vector.ll	test_exhaust_2xlen_rv32_2	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pwadd_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pwaddu_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_padd_h	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_psh1add_h	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_paaddu_h	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_padd_hs_splat_lhs	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_padd_hs_splat_rhs	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-widening-add-acc.ll	test_pwadda_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-widening-add-acc.ll	test_pwaddau_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
srem-vector-lkk.ll	combine_srem_sdiv	`-mtriple=riscv32 -mattr=+m -verify-machineinstrs`
srem-vector-lkk.ll	combine_srem_sdiv	`-mtriple=riscv32 -verify-machineinstrs`
srem-vector-lkk.ll	combine_srem_sdiv	`-mtriple=riscv64 -mattr=+m -verify-machineinstrs`
srem-vector-lkk.ll	combine_srem_sdiv	`-mtriple=riscv64 -verify-machineinstrs`
urem-vector-lkk.ll	combine_urem_udiv	`-mtriple=riscv32 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.ll	combine_urem_udiv	`-mtriple=riscv32 -verify-machineinstrs`
urem-vector-lkk.ll	combine_urem_udiv	`-mtriple=riscv64 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.ll	combine_urem_udiv	`-mtriple=riscv64 -verify-machineinstrs`
calling-conv-p-ext-vector.1218df10d4.ll (mutant of calling-conv-p-ext-vector.ll)	test_exhaust_2xlen_rv32_2	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
calling-conv-p-ext-vector.d5040e51e8.ll (mutant of calling-conv-p-ext-vector.ll)	test_exhaust_2xlen_rv32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-widening-add-acc.167b594017.ll (mutant of rvp-widening-add-acc.ll)	test_pwaddau_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-widening-add-acc.98065af97c.ll (mutant of rvp-widening-add-acc.ll)	test_pwaddau_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-widening-add-acc.c2cc75374f.ll (mutant of rvp-widening-add-acc.ll)	test_pwaddau_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-widening-add-acc.d5abf516c3.ll (mutant of rvp-widening-add-acc.ll)	test_pwaddau_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
srem-vector-lkk.11b78e2aed.ll (mutant of srem-vector-lkk.ll)	combine_srem_sdiv	`-mtriple=riscv64 -mattr=+m -verify-machineinstrs`
srem-vector-lkk.506445107e.ll (mutant of srem-vector-lkk.ll)	combine_srem_sdiv	`-mtriple=riscv32 -verify-machineinstrs`
srem-vector-lkk.7431f79322.ll (mutant of srem-vector-lkk.ll)	combine_srem_sdiv	`-mtriple=riscv64 -verify-machineinstrs`
srem-vector-lkk.76ab0dc271.ll (mutant of srem-vector-lkk.ll)	combine_srem_sdiv	`-mtriple=riscv32 -mattr=+m -verify-machineinstrs`
srem-vector-lkk.87949b4816.ll (mutant of srem-vector-lkk.ll)	combine_srem_sdiv	`-mtriple=riscv32 -mattr=+m -verify-machineinstrs`
srem-vector-lkk.96b7301324.ll (mutant of srem-vector-lkk.ll)	combine_srem_sdiv	`-mtriple=riscv64 -verify-machineinstrs`
srem-vector-lkk.9943ae4273.ll (mutant of srem-vector-lkk.ll)	combine_srem_sdiv	`-mtriple=riscv32 -verify-machineinstrs`
srem-vector-lkk.ce162b9235.ll (mutant of srem-vector-lkk.ll)	combine_srem_sdiv	`-mtriple=riscv64 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.3fe77885b9.ll (mutant of urem-vector-lkk.ll)	combine_urem_udiv	`-mtriple=riscv64 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.4102836829.ll (mutant of urem-vector-lkk.ll)	combine_urem_udiv	`-mtriple=riscv32 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.44f0ee8d7e.ll (mutant of urem-vector-lkk.ll)	combine_urem_udiv	`-mtriple=riscv64 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.7173866482.ll (mutant of urem-vector-lkk.ll)	combine_urem_udiv	`-mtriple=riscv64 -verify-machineinstrs`
urem-vector-lkk.935bdbb5dc.ll (mutant of urem-vector-lkk.ll)	combine_urem_udiv	`-mtriple=riscv32 -verify-machineinstrs`
urem-vector-lkk.b84fd41e1a.ll (mutant of urem-vector-lkk.ll)	combine_urem_udiv	`-mtriple=riscv32 -verify-machineinstrs`
urem-vector-lkk.c47cf9d0bd.ll (mutant of urem-vector-lkk.ll)	combine_urem_udiv	`-mtriple=riscv32 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.d0d9ddcd82.ll (mutant of urem-vector-lkk.ll)	combine_urem_udiv	`-mtriple=riscv64 -verify-machineinstrs`

Generated 2026-10-15 08:05 UTC.