fallback: legalize: G_ASHR <4 x s32>

Run:main-bc8218b282-20261015-074651
Kind:fallback
Category:legalize: G_ASHR <4 x s32>
Occurrences:33 in 24 configs, 10 test files
Snippet from:rvp-simd-64.ll @test_paadd_h via llvm-extract
Config:-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
Local check:reproduces at bc8218b282
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

define <4 x i16> @test_paadd_h(<4 x i16> %a, <4 x i16> %b) {
  %ext.a = sext <4 x i16> %a to <4 x i32>
  %ext.b = sext <4 x i16> %b to <4 x i32>
  %add = add nsw <4 x i32> %ext.a, %ext.b
  %shift = ashr <4 x i32> %add, splat (i32 1)
  %res = trunc <4 x i32> %shift to <4 x i16>
  ret <4 x i16> %res
}

Reproduce:

llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %7:_(<4 x s32>) = G_ASHR %4:_, %5:_(<4 x s32>) (in function: test_paadd_h)
warning: Instruction selection used fallback path for test_paadd_h

Occurrences (33):

InputFunctionConfig
rvp-simd-64.lltest_paadd_h-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_pasub_h-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_pmulh_v4i16-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
smulh.llsmulh_v4i16-mtriple=riscv32 -mattr=+m
smulh.llsmulh_v4i16-mtriple=riscv64 -mattr=+m
calling-conv-sext-zext.3a79735012.ll (mutant of calling-conv-sext-zext.ll)ret_callresult_uint8_as_uint8-mtriple=riscv32 -verify-machineinstrs
double-arith.382e4bfcb3.ll (mutant of double-arith.ll)fmul_d-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
double-arith.681c631eca.ll (mutant of double-arith.ll)fmul_d-mtriple=riscv64 -verify-machineinstrs
double-arith.d0e8001519.ll (mutant of double-arith.ll)fmul_d-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
double-arith.dcdfbe52a9.ll (mutant of double-arith.ll)fmul_d-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64
double-arith.fb408dd7fd.ll (mutant of double-arith.ll)fmul_d-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32
double-arith.ff0aa59896.ll (mutant of double-arith.ll)fmul_d-mtriple=riscv32 -verify-machineinstrs
float-arith.1509ed95a9.ll (mutant of float-arith.ll)fmul_s-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-arith.3f5d151b15.ll (mutant of float-arith.ll)fmul_s-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-arith.6be8dabdb3.ll (mutant of float-arith.ll)fmul_s-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-arith.c3ef1bc760.ll (mutant of float-arith.ll)fmul_s-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-arith.cbf3773989.ll (mutant of float-arith.ll)fmul_s-mtriple=riscv32 -verify-machineinstrs
float-arith.e46b139d97.ll (mutant of float-arith.ll)fmul_s-mtriple=riscv64 -verify-machineinstrs
memmove.20d6962c00.ll (mutant of memmove.ll)unaligned_memmove2-mtriple=riscv32 -mattr=+unaligned-scalar-mem
memmove.26e401ef2f.ll (mutant of memmove.ll)unaligned_memmove2-mtriple=riscv32
memmove.aae461c0c6.ll (mutant of memmove.ll)unaligned_memmove2-mtriple=riscv64
memmove.b85a695472.ll (mutant of memmove.ll)unaligned_memmove2-mtriple=riscv64 -mattr=+unaligned-scalar-mem
rv32zbkb.030a7d3998.ll (mutant of rv32zbkb.ll)pack_i32_3-mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs
rv32zbkb.5fe65d232f.ll (mutant of rv32zbkb.ll)pack_i32_3-mtriple=riscv32 -verify-machineinstrs
rvp-mul-parts-acc-fold.e0f5e55b18.ll (mutant of rvp-mul-parts-acc-fold.ll)macc_h11-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-unaligned-load-store.197eb7afcb.ll (mutant of rvp-unaligned-load-store.ll)test_load_v4i8_align2-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem
rvp-unaligned-load-store.4c5b75b513.ll (mutant of rvp-unaligned-load-store.ll)test_load_v4i8_align2-mtriple=riscv64 -mattr=+experimental-p
rvp-unaligned-load-store.505ab09aaf.ll (mutant of rvp-unaligned-load-store.ll)test_load_v4i8_align2-mtriple=riscv32 -mattr=+experimental-p
rvp-unaligned-load-store.6eac9ed6ca.ll (mutant of rvp-unaligned-load-store.ll)test_load_v4i8_align2-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem
smulh.5f5a520b77.ll (mutant of smulh.ll)smulh_v4i16-mtriple=riscv64 -mattr=+m
smulh.6f80d77fd1.ll (mutant of smulh.ll)smulh_v4i16-mtriple=riscv32 -mattr=+m
xcvbitmanip.5db1dd1a1c.ll (mutant of xcvbitmanip.ll)test.cv.extract1023-O0 -mtriple=riscv32 -mattr=+xcvbitmanip -verify-machineinstrs
xcvbitmanip.66ccd9d81a.ll (mutant of xcvbitmanip.ll)test.cv.extract1023-O3 -mtriple=riscv32 -mattr=+xcvbitmanip -verify-machineinstrs

Generated 2026-10-15 08:05 UTC.