| Input | Function | Config |
|---|
| half-convert.ll | fcvt_q_h | -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs |
| half-convert.ll | fcvt_q_h | -mtriple=riscv32 -mattr=+d -target-abi=ilp32d -verify-machineinstrs |
| half-convert.ll | fcvt_q_h | -mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs -target-abi ilp32d |
| half-convert.ll | fcvt_q_h | -mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi ilp32d |
| half-convert.ll | fcvt_q_h | -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi ilp32f |
| half-convert.ll | fcvt_q_h | -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f |
| half-convert.ll | fcvt_q_h | -mtriple=riscv32 -verify-machineinstrs |
| half-convert.ll | fcvt_q_h | -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs |
| half-convert.ll | fcvt_q_h | -mtriple=riscv64 -mattr=+d -target-abi=lp64d -verify-machineinstrs |
| half-convert.ll | fcvt_q_h | -mtriple=riscv64 -mattr=+d,+zfh -verify-machineinstrs -target-abi lp64d |
| half-convert.ll | fcvt_q_h | -mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi lp64d |
| half-convert.ll | fcvt_q_h | -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi lp64f |
| half-convert.ll | fcvt_q_h | -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f |
| half-convert.ll | fcvt_q_h | -mtriple=riscv64 -verify-machineinstrs |
Generated 2026-10-15 08:05 UTC.