fallback: legalize: G_FSUB <4 x s32>

Run:main-bc8218b282-20261015-074651
Kind:fallback
Category:legalize: G_FSUB <4 x s32> NEW
Occurrences:41 in 25 configs, 14 test files
Snippet from:unaligned-load-store.0d4db1086d.ll (mutant of unaligned-load-store.ll) @merge_stores_i16_i32 via llvm-extract + llvm-reduce
Config:-mtriple=riscv32 -mattr=+unaligned-scalar-mem -verify-machineinstrs
Local check:reproduces at bc8218b282
Compiler Explorer:https://godbolt.org/z/51z1zc48x (llc-assertions-trunk, checked 2026-10-14 11:04 UTC): G reproduces

Snippet:

define <4 x float> @merge_stores_i16_i32() {
  %B = fsub <4 x float> zeroinitializer, zeroinitializer
  ret <4 x float> %B
}

Compiler Explorer panes:

PaneOptionsExitInstsstderr
GlobalISel-mtriple=riscv32 -mattr=+unaligned-scalar-mem -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.*05remark: <unknown>:0:0: unable to legalize instruction: %3:_(<4 x s32>) = G_FSUB %1:_, %1:_ (in function: merge_stores_i16_i32)
warning: Instruction selection used fallback path for merge_stores_i16_i32
SelectionDAG (control)-mtriple=riscv32 -mattr=+unaligned-scalar-mem -verify-machineinstrs -global-isel=005-

Reproduce:

llc -mtriple=riscv32 -mattr=+unaligned-scalar-mem -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+unaligned-scalar-mem -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %3:_(<4 x s32>) = G_FSUB %1:_, %1:_ (in function: merge_stores_i16_i32)
warning: Instruction selection used fallback path for merge_stores_i16_i32

Occurrences (41):

InputFunctionConfig
atomic-rmw-discard.740b65c1dc.ll (mutant of atomic-rmw-discard.ll)amomin_w_discard-O3 -mtriple=riscv64 -mattr=+a -verify-machineinstrs
atomic-rmw-discard.90285c3057.ll (mutant of atomic-rmw-discard.ll)amomin_w_discard-O3 -mtriple=riscv32 -mattr=+a -verify-machineinstrs
calling-conv-sext-zext.beede8811a.ll (mutant of calling-conv-sext-zext.ll)sint8_arg_to_sint8_ret-mtriple=riscv32 -verify-machineinstrs
div-pow2.1f7d595aec.ll (mutant of div-pow2.ll)sdiv64_pow2_65536-mtriple=riscv32 -verify-machineinstrs
div-pow2.edd999acdb.ll (mutant of div-pow2.ll)sdiv64_pow2_65536-mtriple=riscv64 -verify-machineinstrs
half-zfa.52a874698d.ll (mutant of half-zfa.ll)fma_neg_addend-mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfh
half-zfa.68c68b6bdb.ll (mutant of half-zfa.ll)fma_neg_addend-mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfh
memmove.18a31e4f07.ll (mutant of memmove.ll)aligned_memmove2-mtriple=riscv64 -mattr=+unaligned-scalar-mem
memmove.424389d0fc.ll (mutant of memmove.ll)aligned_memmove2-mtriple=riscv32
memmove.70392579ae.ll (mutant of memmove.ll)aligned_memmove2-mtriple=riscv64
memmove.7e2953d029.ll (mutant of memmove.ll)aligned_memmove2-mtriple=riscv32 -mattr=+unaligned-scalar-mem
orc-b-patterns.29d779f4fc.ll (mutant of orc-b-patterns.ll)orc_b_i32_sub_shl8x_x_b1_both_used-mtriple=riscv32 -verify-machineinstrs
orc-b-patterns.389e93c6a1.ll (mutant of orc-b-patterns.ll)orc_b_i32_sub_shl8x_x_b1_both_used-mtriple=riscv64 -verify-machineinstrs
orc-b-patterns.414eb90eb4.ll (mutant of orc-b-patterns.ll)orc_b_i32_sub_shl8x_x_b1_both_used-mtriple=riscv64 -mattr=+zbb -verify-machineinstrs
orc-b-patterns.6a6ae02832.ll (mutant of orc-b-patterns.ll)orc_b_i32_sub_shl8x_x_b1_both_used-mtriple=riscv32 -mattr=+zbb -verify-machineinstrs
rem.859d9c797f.ll (mutant of rem.ll)urem16-mtriple=riscv32 -mattr=+m -verify-machineinstrs
rem.8d7bb016b0.ll (mutant of rem.ll)urem16-mtriple=riscv64 -verify-machineinstrs
rem.8ee5bbd270.ll (mutant of rem.ll)urem16-mtriple=riscv32 -verify-machineinstrs
rem.ec17b1875e.ll (mutant of rem.ll)urem16-mtriple=riscv64 -mattr=+m -verify-machineinstrs
rv64i-exhaustive-w-insts.065232710c.ll (mutant of rv64i-exhaustive-w-insts.ll)sext_sraw_zext_aext-mtriple=riscv64 -verify-machineinstrs -mattr=+zba
rv64i-exhaustive-w-insts.b2de0438e6.ll (mutant of rv64i-exhaustive-w-insts.ll)sext_sraw_zext_aext-mtriple=riscv64 -verify-machineinstrs
shifts.8426544a06.ll (mutant of shifts.ll)lshr128_shamt32-mtriple=riscv64 -verify-machineinstrs
shifts.ab7eb01f83.ll (mutant of shifts.ll)lshr128_shamt32-mtriple=riscv32 -verify-machineinstrs
shlimm-addimm.4f22a6ba53.ll (mutant of shlimm-addimm.ll)shl5_sub47968_c-mtriple=riscv32 -verify-machineinstrs
shlimm-addimm.d272986f0c.ll (mutant of shlimm-addimm.ll)shl5_sub47968_c-mtriple=riscv64 -verify-machineinstrs
stack-realignment.11e191db4f.ll (mutant of stack-realignment.ll)caller2048-mtriple=riscv32 -verify-machineinstrs
stack-realignment.8412a8a7b4.ll (mutant of stack-realignment.ll)caller2048-mtriple=riscv64 -target-abi lp64e -verify-machineinstrs
stack-realignment.c7020750df.ll (mutant of stack-realignment.ll)caller2048-mtriple=riscv64 -verify-machineinstrs
stack-realignment.dfe7632c88.ll (mutant of stack-realignment.ll)caller2048-mtriple=riscv32 -target-abi ilp32e -verify-machineinstrs
unaligned-load-store.0d4db1086d.ll (mutant of unaligned-load-store.ll)merge_stores_i16_i32-mtriple=riscv32 -mattr=+unaligned-scalar-mem -verify-machineinstrs
unaligned-load-store.0dc86ea1ce.ll (mutant of unaligned-load-store.ll)merge_stores_i16_i32-mtriple=riscv64 -mattr=+unaligned-scalar-mem -verify-machineinstrs
unaligned-load-store.105499ab37.ll (mutant of unaligned-load-store.ll)merge_stores_i16_i32-mtriple=riscv64 -verify-machineinstrs
unaligned-load-store.48794a836c.ll (mutant of unaligned-load-store.ll)merge_stores_i16_i32-mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs
unaligned-load-store.b17cd5d566.ll (mutant of unaligned-load-store.ll)merge_stores_i16_i32-mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs
unaligned-load-store.d261703ca8.ll (mutant of unaligned-load-store.ll)merge_stores_i16_i32-mtriple=riscv32 -verify-machineinstrs
xqcibm-insert.74df28d2de.ll (mutant of xqcibm-insert.ll)no_bseti_1-mtriple=riscv32 -verify-machineinstrs
xqcibm-insert.970ec37e04.ll (mutant of xqcibm-insert.ll)no_bseti_1-mtriple=riscv32 -mattr=+xqcibm -verify-machineinstrs
xqcibm-insert.e1a2f319f1.ll (mutant of xqcibm-insert.ll)no_bseti_1-mtriple=riscv32 -mattr=+xqcibm,+zbs -verify-machineinstrs
xqcisls.407d069690.ll (mutant of xqcisls.ll)srh-mtriple=riscv32 -verify-machineinstrs
xqcisls.957fba15c9.ll (mutant of xqcisls.ll)srh-mtriple=riscv32 -mattr=+zba,+xqcisls -verify-machineinstrs
xqcisls.c1d54cbcd6.ll (mutant of xqcisls.ll)srh-mtriple=riscv32 --mattr=+zba -verify-machineinstrs

Generated 2026-10-15 08:05 UTC.