fallback: legalize: G_IMPLICIT

fallback: legalize: G_IMPLICIT_DEF <4 x s8>

Run:	main-bc8218b282-20261015-074651
Kind:	fallback
Category:	legalize: G_IMPLICIT_DEF <4 x s8>
Occurrences:	139 in 3 configs, 8 test files
Snippet from:	rvp-narrowing-zip.ll @test_pnzip_v4i8 via llvm-extract
Config:	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
Local check:	reproduces at bc8218b282
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

define <4 x i8> @test_pnzip_v4i8(<2 x i16> %a, <2 x i16> %b) {
  %ca = bitcast <2 x i16> %a to <4 x i8>
  %cb = bitcast <2 x i16> %b to <4 x i8>
  %r = shufflevector <4 x i8> %ca, <4 x i8> %cb, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
  ret <4 x i8> %r
}

Reproduce:

llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %15:_(<4 x s8>) = G_IMPLICIT_DEF (in function: test_pnzip_v4i8)
warning: Instruction selection used fallback path for test_pnzip_v4i8

Occurrences (139) (first 50):

Input	Function	Config
calling-conv-p-ext-vector.ll	test_cc_v4i8	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
calling-conv-p-ext-vector.ll	test_call_v4i8	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-bitreverse-zbkb.ll	test_bitreverse_v4i8	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb,+zbkb -verify-machineinstrs`
rvp-narrowing-clip.ll	pnclipu_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-clip.ll	pnclipru_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-clip.ll	pnclip_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-clip.ll	pnclipr_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-clip.ll	pnclipu_v4i8_15	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-clip.ll	pnclipu_v4i8_16	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-clip.ll	pnclipu_v4i8_0	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-clip.ll	pnclipu_v4i8_8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-clip.ll	pnclipru_v4i8_17	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-shift.ll	pnsrl_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-shift.ll	pnsra_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-shift.ll	pnsrar_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-shift.ll	pnsrl_v4i8_15	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-shift.ll	pnsrl_v4i8_16	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-shift.ll	pnsrl_v4i8_32	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-shift.ll	pnsrar_v4i8_15	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-shift.ll	pnsrar_v4i8_16	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-narrowing-zip.ll	test_pnzip_v4i8	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-narrowing-zip.ll	test_pnziph_v4i8	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_padd_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_psub_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_and_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_or_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_xor_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_andn_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_orn_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_xnor_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_not_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_psadd_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_psaddu_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pssub_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pssubu_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_paadd_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_paaddu_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pabs_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pdif_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pdifu_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pasub_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pasubu_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_insert_vector_8	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_insert_vector_8_elem2	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pslli_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_psslai_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_psrli_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_psrai_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_psll_bs_vec_shamt	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_psrl_bs_vec_shamt	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`

Generated 2026-10-15 08:05 UTC.