fallback: legalize: G_INSERT_SUBVECTOR <vscale x 8 x s8>,<16 x s8>

Run:main-bc8218b282-20261015-074651
Kind:fallback
Category:legalize: G_INSERT_SUBVECTOR <vscale x 8 x s8>,<16 x s8>
Occurrences:10 in 2 configs, 1 test files
Snippet from:nontemporal.ll @test_nontemporal_load_v16i8 via llvm-extract
Config:-mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v
Local check:reproduces at bc8218b282
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

define <16 x i8> @test_nontemporal_load_v16i8(ptr %p) {
  %1 = load <16 x i8>, ptr %p, align 16, !nontemporal !0
  ret <16 x i8> %1
}

!0 = !{i32 1}

Reproduce:

llc -mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %3:_(<vscale x 8 x s8>) = G_INSERT_SUBVECTOR %2:_, %1:_(<16 x s8>), 0 (in function: test_nontemporal_load_v16i8)
warning: Instruction selection used fallback path for test_nontemporal_load_v16i8

Occurrences (10):

InputFunctionConfig
nontemporal.lltest_nontemporal_load_v16i8-mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_P1_load_v16i8-mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_PALL_load_v16i8-mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_S1_load_v16i8-mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_ALL_load_v16i8-mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_load_v16i8-mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_P1_load_v16i8-mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_PALL_load_v16i8-mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_S1_load_v16i8-mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_ALL_load_v16i8-mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v

Generated 2026-10-15 08:05 UTC.