fallback: legalize: G_INTRINSIC

fallback: legalize: G_INTRINSIC_ROUND s16

Run:	main-bc8218b282-20261015-074651
Kind:	fallback
Category:	legalize: G_INTRINSIC_ROUND s16
Occurrences:	104 in 20 configs, 3 test files
Snippet from:	half-round-conv.ll @test_round_si8 via llvm-extract
Config:	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
Local check:	reproduces at bc8218b282
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

define signext i8 @test_round_si8(half %x) {
  %a = call half @llvm.round.f16(half %x)
  %b = fptosi half %a to i8
  ret i8 %b
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare half @llvm.round.f16(half) #0

attributes #0 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %1:_(s16) = G_INTRINSIC_ROUND %0:_ (in function: test_round_si8)
warning: Instruction selection used fallback path for test_round_si8

Occurrences (104) (first 50):

Input	Function	Config
half-intrinsics.ll	round_f16	`-mtriple=riscv32 -mattr=+d -mattr=+zfh -verify-machineinstrs -target-abi ilp32d`
half-intrinsics.ll	round_f16	`-mtriple=riscv32 -mattr=+d -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32d`
half-intrinsics.ll	round_f16	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi ilp32f`
half-intrinsics.ll	round_f16	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f`
half-intrinsics.ll	round_f16	`-mtriple=riscv32 -verify-machineinstrs`
half-intrinsics.ll	round_f16	`-mtriple=riscv64 -mattr=+d -mattr=+zfh -verify-machineinstrs -target-abi lp64d`
half-intrinsics.ll	round_f16	`-mtriple=riscv64 -mattr=+d -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d`
half-intrinsics.ll	round_f16	`-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi lp64f`
half-intrinsics.ll	round_f16	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f`
half-intrinsics.ll	round_f16	`-mtriple=riscv64 -verify-machineinstrs`
half-round-conv.ll	test_round_si8	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_si16	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_si32	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_si64	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_ui8	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_ui16	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_ui32	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_ui64	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_half	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_si8	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_si16	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_si32	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_si64	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_ui8	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_ui16	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_ui32	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_ui64	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_half	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv.ll	test_round_si8	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_si16	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_si32	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_si64	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_ui8	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_ui16	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_ui32	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_ui64	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_half	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_si8	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_si16	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_si32	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_si64	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_ui8	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_ui16	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_ui32	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_ui64	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_half	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv.ll	test_round_si8	`-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi=lp64f`
half-round-conv.ll	test_round_si16	`-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi=lp64f`
half-round-conv.ll	test_round_si32	`-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi=lp64f`
half-round-conv.ll	test_round_si64	`-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi=lp64f`

Generated 2026-10-15 08:05 UTC.