fallback: legalize: G_LOAD <8 x s8>,p0

Run:	main-bc8218b282-20261015-074651
Kind:	fallback
Category:	legalize: G_LOAD <8 x s8>,p0
Occurrences:	310 in 207 configs, 76 test files
Snippet from:	rvp-unaligned-load-store.ll @test_store_v4i8_align1 via llvm-extract
Config:	`-mtriple=riscv32 -mattr=+experimental-p`
Local check:	reproduces at bc8218b282
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

define void @test_store_v4i8_align1(ptr %a_ptr, ptr %b_ptr) {
  %a = load <8 x i8>, ptr %a_ptr, align 8
  store <8 x i8> %a, ptr %b_ptr, align 1
  ret void
}

Reproduce:

llc -mtriple=riscv32 -mattr=+experimental-p -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+experimental-p -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(<8 x s8>) = G_LOAD %0:_(p0) :: (load (<8 x s8>) from %ir.a_ptr) (in function: test_store_v4i8_align1)
warning: Instruction selection used fallback path for test_store_v4i8_align1

Occurrences (310) (first 50):

Input	Function	Config
rvp-unaligned-load-store.ll	test_store_v4i8_align1	`-mtriple=riscv32 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v4i8_align2	`-mtriple=riscv32 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v4i8_align4	`-mtriple=riscv32 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v8i8_align1	`-mtriple=riscv32 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v8i8_align2	`-mtriple=riscv32 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_load_v4i8_align1	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i8_align1	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v4i8_align2	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i8_align2	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v4i8_align4	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i8_align4	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v8i8_align1	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v8i8_align1	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v8i8_align2	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v8i8_align2	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i8_align1	`-mtriple=riscv64 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v4i8_align2	`-mtriple=riscv64 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v4i8_align4	`-mtriple=riscv64 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v8i8_align1	`-mtriple=riscv64 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v8i8_align2	`-mtriple=riscv64 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_load_v4i8_align1	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i8_align1	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v4i8_align2	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i8_align2	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v4i8_align4	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i8_align4	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v8i8_align1	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v8i8_align1	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v8i8_align2	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v8i8_align2	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
aext.015331a828.ll (mutant of aext.ll)	aext	`-mtriple=riscv32 -verify-machineinstrs`
aext.2d221a299c.ll (mutant of aext.ll)	aext	`-mtriple=riscv64 -verify-machineinstrs`
align.8d2692c4d0.ll (mutant of align.ll)	foo	`-mtriple=riscv32 -mattr=+c -verify-machineinstrs`
align.f193c107f8.ll (mutant of align.ll)	foo	`-mtriple=riscv32 -verify-machineinstrs`
atomic-cmpxchg-flag.a2feb4a6d4.ll (mutant of atomic-cmpxchg-flag.ll)	cmpxchg_i32_seq_cst_seq_cst	`-mtriple=riscv64 -mattr=+a -verify-machineinstrs`
attributes-andes.01b2deb70d.ll (mutant of attributes-andes.ll)	addi	`-mtriple=riscv32 -mattr=+xandesvsinth`
attributes-andes.052f2abc79.ll (mutant of attributes-andes.ll)	addi	`-mtriple=riscv64 -mattr=+xandesbfhcvt`
attributes-andes.17802f5419.ll (mutant of attributes-andes.ll)	addi	`-mtriple=riscv32 -mattr=+xandesvsintload`
attributes-andes.20789f8485.ll (mutant of attributes-andes.ll)	addi	`-mtriple=riscv64 -mattr=+xandesvdot`
attributes-andes.3cf6875c7c.ll (mutant of attributes-andes.ll)	addi	`-mtriple=riscv32 -mattr=+xandesbfhcvt`
attributes-andes.45a3f1afd1.ll (mutant of attributes-andes.ll)	addi	`-mtriple=riscv32 -mattr=+xandesvbfhcvt`
attributes-andes.5b494e0b62.ll (mutant of attributes-andes.ll)	addi	`-mtriple=riscv64 -mattr=+xandesvpackfph`
attributes-andes.80e073ee41.ll (mutant of attributes-andes.ll)	addi	`-mtriple=riscv64 -mattr=+xandesvsinth`
attributes-andes.b997861f7d.ll (mutant of attributes-andes.ll)	addi	`-mtriple=riscv32 -mattr=+xandesvdot`
attributes-andes.dcafc63d2f.ll (mutant of attributes-andes.ll)	addi	`-mtriple=riscv64 -mattr=+xandesvsintload`
attributes-andes.dcee63c406.ll (mutant of attributes-andes.ll)	addi	`-mtriple=riscv64 -mattr=+xandesperf`
attributes-andes.ecedbb5195.ll (mutant of attributes-andes.ll)	addi	`-mtriple=riscv32 -mattr=+xandesperf`
attributes-andes.ed07da32fa.ll (mutant of attributes-andes.ll)	addi	`-mtriple=riscv32 -mattr=+xandesvpackfph`
attributes-andes.fd23504a97.ll (mutant of attributes-andes.ll)	addi	`-mtriple=riscv64 -mattr=+xandesvbfhcvt`
attributes-module-flag.19232d715a.ll (mutant of attributes-module-flag.ll)	addi	`-mtriple=riscv64`

Generated 2026-10-15 08:05 UTC.