fallback: legalize: G_VECREDUCE_FMIN s32,<4 x s32>

Run:main-bc8218b282-20261015-074651
Kind:fallback
Category:legalize: G_VECREDUCE_FMIN s32,<4 x s32>
Occurrences:8 in 2 configs, 1 test files
Snippet from:double_reduct.ll @fmin_f32 via llvm-extract
Config:-mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs
Local check:reproduces at bc8218b282
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

define float @fmin_f32(<4 x float> %a, <4 x float> %b) {
  %r1 = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)
  %r2 = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %b)
  %r = call float @llvm.minnum.f32(float %r1, float %r2)
  ret float %r
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare float @llvm.minnum.f32(float, float) #0

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>) #0

attributes #0 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %5:_(s32) = nnan ninf nsz arcp contract afn reassoc G_VECREDUCE_FMIN %1:_(<4 x s32>) (in function: fmin_f32)
warning: Instruction selection used fallback path for fmin_f32

Occurrences (8):

InputFunctionConfig
double_reduct.llfmin_f32-mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs
double_reduct.llfmin_f32-mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d -verify-machineinstrs
double_reduct.2e5066af6b.ll (mutant of double_reduct.ll)fmin_f32-mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs
double_reduct.5b18065f7b.ll (mutant of double_reduct.ll)fmin_f32-mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs
double_reduct.a051090e90.ll (mutant of double_reduct.ll)fmin_f32-mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d -verify-machineinstrs
double_reduct.b13efc7ace.ll (mutant of double_reduct.ll)fmin_f32-mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d -verify-machineinstrs
double_reduct.bec42cb2a7.ll (mutant of double_reduct.ll)fmin_f32-mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d -verify-machineinstrs
double_reduct.ec04e7b6eb.ll (mutant of double_reduct.ll)fmin_f32-mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs

Generated 2026-10-15 08:05 UTC.