fallback: translate: lshr <vscale x 2 x i32>

Run:main-bc8218b282-20261015-074651
Kind:fallback
Category:translate: lshr <vscale x 2 x i32>
Occurrences:8 in 2 configs, 1 test files
Snippet from:and-add-lsr.ll @and_add_lsr_vec2 via llvm-extract
Config:-mtriple=riscv32 -verify-machineinstrs -mattr=+v
Local check:reproduces at bc8218b282
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

define <vscale x 2 x i32> @and_add_lsr_vec2(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {
  %1 = add <vscale x 2 x i32> %x, splat (i32 4095)
  %2 = lshr <vscale x 2 x i32> %y, splat (i32 20)
  %r = and <vscale x 2 x i32> %2, %1
  ret <vscale x 2 x i32> %r
}

Reproduce:

llc -mtriple=riscv32 -verify-machineinstrs -mattr=+v -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -verify-machineinstrs -mattr=+v -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to translate instruction: lshr: '  %2 = lshr <vscale x 2 x i32> %y, splat (i32 20)' (in function: and_add_lsr_vec2)
warning: Instruction selection used fallback path for and_add_lsr_vec2

Occurrences (8):

InputFunctionConfig
and-add-lsr.lland_add_lsr_vec2-mtriple=riscv32 -verify-machineinstrs -mattr=+v
and-add-lsr.lland_add_lsr_vec2-mtriple=riscv64 -verify-machineinstrs -mattr=+v
and-add-lsr.52bdbe34a3.ll (mutant of and-add-lsr.ll)and_add_lsr_vec2-mtriple=riscv64 -verify-machineinstrs -mattr=+v
and-add-lsr.5e9315d7b9.ll (mutant of and-add-lsr.ll)and_add_lsr_vec2-mtriple=riscv32 -verify-machineinstrs -mattr=+v
and-add-lsr.7dc5422126.ll (mutant of and-add-lsr.ll)and_add_lsr_vec2-mtriple=riscv64 -verify-machineinstrs -mattr=+v
and-add-lsr.983f17f7bd.ll (mutant of and-add-lsr.ll)and_add_lsr_vec2-mtriple=riscv64 -verify-machineinstrs -mattr=+v
and-add-lsr.be20035c59.ll (mutant of and-add-lsr.ll)and_add_lsr_vec2-mtriple=riscv32 -verify-machineinstrs -mattr=+v
and-add-lsr.d58a6833d3.ll (mutant of and-add-lsr.ll)and_add_lsr_vec2-mtriple=riscv32 -verify-machineinstrs -mattr=+v

Generated 2026-10-15 08:05 UTC.