regression: +56 insts: lshr_16bytes (wide-scalar-shift-legalization.ll)

Snippet:

; Function Attrs: nounwind
define void @lshr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) #0 {
  %A = alloca i128, align 8
  store i128 poison, ptr %A, align 4
  %src = load i128, ptr %src.ptr, align 1
  %bitOff = load i128, ptr %bitOff.ptr, align 1
  %res = lshr i128 %src, %bitOff
  store i128 %res, ptr %dst, align 1
  store i128 %bitOff, ptr %A, align 4
  ret void
}

attributes #0 = { nounwind }

Reproduce:

llc -mtriple=riscv32 -verify-machineinstrs -global-isel snippet.ll -o -
llc -mtriple=riscv32 -verify-machineinstrs -global-isel=0 snippet.ll -o -

Assembly diff (SelectionDAG vs GlobalISel):

--- sdag
+++ gisel
@@ -1,146 +1,221 @@
-addi sp, sp, -48
-lbu a3, 5(a1)
-lbu a4, 1(a0)
-lbu a5, 0(a0)
+addi sp, sp, -64
+sw s0, 60(sp)
+sw s1, 56(sp)
+sw s2, 52(sp)
+sw s3, 48(sp)
+sw s4, 44(sp)
+sw s5, 40(sp)
+sw s6, 36(sp)
+sw s7, 32(sp)
+sw s8, 28(sp)
+sw s9, 24(sp)
+lbu a3, 0(a0)
+lbu a4, 3(a0)
+lbu t3, 1(a0)
 lbu a6, 2(a0)
-lbu a7, 3(a0)
+lbu a7, 7(a0)
+lbu t0, 8(a0)
+lbu t1, 9(a0)
+lbu t2, 11(a0)
+lbu t4, 10(a0)
 slli a4, a4, 8
-lbu t0, 5(a0)
-lbu t1, 6(a0)
-lbu t2, 7(a0)
-lbu t3, 4(a0)
-or a4, a4, a5
+lbu a5, 4(a0)
+lbu t5, 5(a0)
+lbu t6, 6(a0)
+or a6, a4, a6
+slli a7, a7, 8
+slli t2, t2, 8
+slli t1, t1, 8
+or a4, t2, t4
+or t0, t1, t0
+slli a4, a4, 16
+lbu t1, 12(a0)
+lbu t2, 13(a0)
+lbu t4, 14(a0)
+lbu a0, 15(a0)
+or a7, a7, t6
+or a4, a4, t0
+lbu t6, 0(a1)
+lbu s0, 1(a1)
+lbu s1, 2(a1)
+lbu s2, 3(a1)
+slli t2, t2, 8
+slli a0, a0, 8
+or t1, t2, t1
+or a0, a0, t4
+slli t3, t3, 8
+slli t0, t5, 8
+slli a0, a0, 16
+slli s2, s2, 8
+slli s0, s0, 8
+or t2, s2, s1
+or t4, s0, t6
+slli t2, t2, 16
+or t1, a0, t1
+or a0, t2, t4
+li t2, 32
+neg t6, a0
+srl t4, a4, a0
+sll s0, t1, t6
+bltu a0, t2, .L0
+srl t5, t1, a0
+j .L1
+.L0:
+or t5, t4, s0
+.L1:
+or t3, t3, a3
 slli a6, a6, 16
-slli a7, a7, 24
-or a5, a7, a6
-slli t0, t0, 8
-slli t1, t1, 16
-slli t2, t2, 24
-lbu a6, 8(a0)
-lbu a7, 9(a0)
-or t0, t0, t3
-or t1, t2, t1
-or a4, a5, a4
-or a5, t1, t0
-lbu t0, 10(a0)
-lbu t1, 11(a0)
-slli a7, a7, 8
-lbu t2, 13(a0)
-or a6, a7, a6
-lbu a7, 12(a0)
-lbu t3, 14(a0)
-lbu a0, 15(a0)
-slli t0, t0, 16
-slli t1, t1, 24
-or t0, t1, t0
-slli t2, t2, 8
-or a6, t0, a6
-or a7, t2, a7
-slli t3, t3, 16
-slli a0, a0, 24
-or a0, a0, t3
-lbu t0, 4(a1)
-lbu t1, 6(a1)
-lbu t2, 7(a1)
-or a7, a0, a7
-slli a3, a3, 8
-lbu t3, 8(a1)
-lbu t4, 9(a1)
-lbu t5, 10(a1)
-lbu t6, 11(a1)
-slli t1, t1, 16
-slli t2, t2, 24
-or a0, a3, t0
-or a3, t2, t1
-or a0, a3, a0
-slli t4, t4, 8
-slli t5, t5, 16
-slli t6, t6, 24
-or a3, t4, t3
-or t0, t6, t5
-or a3, t0, a3
-lbu t0, 1(a1)
-lbu t1, 13(a1)
-lbu t2, 0(a1)
-lbu t3, 2(a1)
-lbu t4, 3(a1)
-lbu t5, 12(a1)
-lbu t6, 14(a1)
-lbu a1, 15(a1)
-slli t0, t0, 8
-or t0, t0, t2
-slli t1, t1, 8
-slli t3, t3, 16
-slli t4, t4, 24
-slli t6, t6, 16
-or t2, t4, t3
-slli t3, a1, 24
-or a1, t2, t0
-srli t0, a1, 3
-sw zero, 16(sp)
-sw zero, 20(sp)
-sw zero, 24(sp)
-sw zero, 28(sp)
-andi t0, t0, 12
-mv t2, sp
-sw a4, 0(sp)
-sw a5, 4(sp)
-sw a6, 8(sp)
-sw a7, 12(sp)
-add t0, t2, t0
-lw a5, 4(t0)
-lw a6, 8(t0)
-or a4, t1, t5
-or a7, t3, t6
-or a4, a7, a4
-andi a7, a1, 31
-xori a7, a7, 31
-lw t1, 0(t0)
-lw t0, 12(t0)
-slli t2, a6, 1
-srl t3, a5, a1
-sll t2, t2, a7
-or t2, t3, t2
-slli a5, a5, 1
-srl t1, t1, a1
-sll a5, a5, a7
-or a5, t1, a5
-slli t1, t0, 1
-srl a6, a6, a1
-sll a7, t1, a7
-or a6, a6, a7
-srl a7, t0, a1
-srli t0, a7, 24
-srli t1, a7, 16
-srli t3, a7, 8
-sb a7, 12(a2)
-sb t3, 13(a2)
-sb t1, 14(a2)
-sb t0, 15(a2)
-srli a7, a6, 24
-srli t0, a6, 16
-srli t1, a6, 8
-sb a6, 8(a2)
-sb t1, 9(a2)
-sb t0, 10(a2)
-sb a7, 11(a2)
-srli a6, a5, 24
-srli a7, a5, 16
-srli t0, a5, 8
-sb a5, 0(a2)
-sb t0, 1(a2)
-sb a7, 2(a2)
-sb a6, 3(a2)
-srli a5, t2, 24
-srli a6, t2, 16
-srli a7, t2, 8
-sb t2, 4(a2)
-sb a7, 5(a2)
-sb a6, 6(a2)
-sb a5, 7(a2)
-sw a1, 32(sp)
-sw a0, 36(sp)
-sw a3, 40(sp)
-sw a4, 44(sp)
-addi sp, sp, 48
+or a5, t0, a5
+slli t0, a7, 16
+mv a3, a4
+beqz a0, .L2
+mv a3, t5
+.L2:
+or a7, a6, t3
+or a6, t0, a5
+bltu a0, t2, .L3
+li a5, 0
+srl t5, a6, a0
+j .L4
+.L3:
+srl t0, a7, a0
+sll t3, a6, t6
+srl a5, t1, a0
+or t5, t0, t3
+.L4:
+li t0, 64
+mv t3, a7
+beqz a0, .L5
+mv t3, t5
+.L5:
+sub s2, t0, a0
+bltu a0, t2, .L6
+li t5, 0
+bgeu s2, t2, .L7
+.L8:
+neg s1, s2
+srl s1, a4, s1
+sll t6, a4, t6
+or s3, s1, s0
+j .L9
+.L6:
+srl t5, a6, a0
+bltu s2, t2, .L8
+.L7:
+li t6, 0
+sll s3, a4, s2
+.L9:
+addi s1, a0, -64
+mv s0, t1
+beqz s2, .L10
+mv s0, s3
+.L10:
+bltu s1, t2, .L11
+srl t4, t1, s1
+j .L12
+.L11:
+neg s2, s1
+sll s2, t1, s2
+or t4, t4, s2
+.L12:
+lbu s9, 7(a1)
+lbu s8, 11(a1)
+lbu s7, 15(a1)
+beqz s1, .L13
+mv a4, t4
+.L13:
+lbu t4, 5(a1)
+lbu s4, 6(a1)
+lbu s3, 9(a1)
+lbu s2, 10(a1)
+lbu s6, 13(a1)
+lbu s5, 14(a1)
+slli s9, s9, 8
+slli s8, s8, 8
+slli s7, s7, 8
+bltu s1, t2, .L14
+li t1, 0
+j .L15
+.L14:
+srl t1, t1, a0
+.L15:
+lbu t2, 4(a1)
+lbu s1, 8(a1)
+lbu a1, 12(a1)
+or s4, s9, s4
+slli s9, t4, 8
+slli s3, s3, 8
+or s2, s8, s2
+slli s6, s6, 8
+or t4, s7, s5
+bgeu a0, t0, .L16
+or a4, t3, t6
+or t1, t5, s0
+.L16:
+or t2, s9, t2
+slli s4, s4, 16
+or t3, s3, s1
+slli s2, s2, 16
+or t5, s6, a1
+slli t4, t4, 16
+beqz a0, .L17
+mv a7, a4
+mv a6, t1
+.L17:
+or a1, s4, t2
+or a4, s2, t3
+or t1, t4, t5
+bltu a0, t0, .L18
+li a3, 0
+li a5, 0
+.L18:
+lui t0, 16
+addi t0, t0, -1
+srli t2, a7, 16
+and t3, a7, t0
+srli t4, a7, 24
+srli t3, t3, 8
+sb a7, 0(a2)
+sb t3, 1(a2)
+sb t2, 2(a2)
+sb t4, 3(a2)
+srli a7, a6, 16
+and t2, a6, t0
+srli t2, t2, 8
+srli t3, a6, 24
+sb a6, 4(a2)
+sb t2, 5(a2)
+sb a7, 6(a2)
+sb t3, 7(a2)
+srli a6, a3, 16
+and a7, a3, t0
+srli a7, a7, 8
+srli t2, a3, 24
+sb a3, 8(a2)
+sb a7, 9(a2)
+sb a6, 10(a2)
+sb t2, 11(a2)
+srli a3, a5, 16
+and a6, a5, t0
+srli a6, a6, 8
+srli a7, a5, 24
+sb a5, 12(a2)
+sb a6, 13(a2)
+sb a3, 14(a2)
+sb a7, 15(a2)
+sw a0, 8(sp)
+sw a1, 12(sp)
+sw a4, 16(sp)
+sw t1, 20(sp)
+lw s0, 60(sp)
+lw s1, 56(sp)
+lw s2, 52(sp)
+lw s3, 48(sp)
+lw s4, 44(sp)
+lw s5, 40(sp)
+lw s6, 36(sp)
+lw s7, 32(sp)
+lw s8, 28(sp)
+lw s9, 24(sp)
+addi sp, sp, 64
 ret

Occurrences (1):

Generated 2026-10-15 08:05 UTC.